1. Field of the Invention
This invention generally relates to dual power supply input/output circuits that are at an interface of circuits having a low voltage power supply and circuits having a high voltage power supply. More particularly, this invention relates to circuits or subcircuits that will protect the input/output circuits from damage due to improper exposure to the high voltage power supply.
2. Description of the Related Art
An interface buffer circuit as shown in FIG. 1 is well understood by those skilled in the art. The n-channel Metal Oxide Semiconductor (MOS) driver transistor M1 has a source connected to the substrate biasing voltage source (VSS). The substrate biasing voltage source (VSS) is also often a ground reference point. The drain of the n-channel MOS driver transistor M1 is connected to the input/output pad to transfer signals from circuits having a low voltage power supply VDDL to circuits having a high voltage power supply VDDH.
The p-channel MOS driver transistor M2 has a source connected to an input/output power supply voltage source VDDI/O. The input/output power supply voltage source VDDI/O may be the low voltage power supply VDDL, the high voltage power supply VDDH, or a low voltage isolated power supply that is separate from the low voltage power supply VDDL connected to the internal circuits. The p-channel MOS driver transistor M2 further has a drain connected to the input/output pad.
The voltage level VI/O at the drains of the n-channel and the p-channel MOS driver transistors M1 and M2 will be at the voltage level approaching that of the substrate biasing voltage source VSS, when the voltage level at the gate of the n-channel MOS driver transistor M1 is at a voltage level of the low voltage power supply VDDL. The voltage level VI/O at the drains of the n-channel and the p-channel MOS driver transistor M1 and M2 will be at the voltage approaching that of the input/output power supply VDDI/O, when the voltage level at the gate of the p-channel MOS driver transistor M2 is at a voltage level approaching that of the substrate biasing voltage source VSS.
The source of the n-channel MOS transistor M5 is connected to the substrate biasing voltage source VSS. The source of the p-channel MOS transistor M7 is connected to the low voltage power supply VDDL.
The gates of the n-channel and the p-channel MOS transistor M5 and M7 are connected to the input terminal VIN. The input terminal VIN transfers the signals from the circuits having the low voltage power supply VDDL.
The drains of the n-channel and p-channel MOS transistor M5 and M7 are connected to the gates of the n-channel and p-channel MOS driver transistors M1 and M2. The voltage level V1 will approach that of the substrate biasing voltage source VSS, when the input terminal VIN and thus the gates of the n-channel and p-channel MOS transistors M5 and M7 are at a voltage level approaching that of the low voltage power supply VDDL. The voltage level V1 will approach that of the low voltage power supply VDDL, when the input terminal and thus the gates of the n-channel and p-channel MOS transistors M5 and M7 are at a voltage level approaching that of the substrate biasing voltage source VSS.
The n-channel and p-channel MOS transistors M5 and M7 form the predriver circuit PDrv. The n-channel and p-channel MOS driver transistors M1 and M2 form the interface driver circuit IDrv.
If the design of the n-channel MOS driver transistor M1 is such that the gate oxide deposited over the channel that is between the implanted n-type source and drain has a thickness equivalent to that of the circuits having the low voltage power supply and the voltage level VI/O at the drain of the n-channel MOS driver transistor M1 is approaching that of the high voltage power supply VDDH, the voltage field across the gate oxide can cause damage to the gate oxide. The voltage level VI/O can reach the high voltage higher voltage levels due to ground bounce due to reflections or mismatching of the termination structure.
It will be understood by those skilled in the art, that the voltage level VI/O at the drain of the n-channel MOS driver transistor M1 is determined by the termination structure of external circuitry connected to the input/output pad. It is possible that under certain termination configurations, the voltage level VI/O may equal twice the voltage level of the input/output power supply voltage source VDDI/O.
While the description as presented in FIG. 1 is for a "single ended" transmission scheme, it will further be apparent to those skilled in the art that a predriver PDrv can control the gate of the n-channel MOS driver transistor M1 and a separate predriver circuit PDrv2 (not shown) can control the gate of the p-channel MOS driver transistor M2. This configuration as a "tri-state buffer", connected with a receiver circuit, allows, circuit to function on a bi-directional bus structure that is well known in the art.
With both the n-channel MOS driver transistor M1 and the p-channel MOS driver transistor M2 turned off, the voltage level VI/O can reach a voltage level that is also twice that of the input/output power supply voltage source VDDI/O. Again, it is apparent that with the voltage level VI/O at a large level, the voltage field across the gate oxide of the n-channel MOS driver transistor M1 will cause damage to the gate oxide as described above.
U.S. Pat. No. 5,721,656 (Wu et al.) describes an electrostatic discharge protection network which diverts ESD stress arising between any two contact pads of an IC device, in order to prevent damage to the internal circuitry of the IC device. An ESD discharge bus is arranged around the periphery of an IC chip. Between each IC pad and the discharge bus, there is a protection circuit to directly bypass an ESD stress arising at any two IC pads. Each ESD protection circuit includes a diode, a thick-oxide device, a resistor, and a capacitor. The protection circuit is operated in snapback mode without causing breakdown. Therefore, the triggering voltage of the ESD protection circuit is lowered to the level of the snapback voltage but not to the level of the breakdown voltage.
U.S. Pat. No. 5,671,111 (Chen) teaches an electrostatic discharge (ESD) protection circuitry with a gate-capacitor-coupled device and a silicon controlled rectifier (SCR) coupled to an output of an output device in a sub micron metal oxide semiconductor circuit is disclosed. The gate-capacitor-coupled device has a lower ESD breakdown voltage than an output device, hence, the gate-capacitor-coupled device breaks down and causes the SCR to breakdown when a destructive ESD voltage impinges on the output of the output device. The SCR upon breaking down, discharges the destructive ESD to the power supply bus VDD or VSS.
U.S. Pat. No. 5,631,793 (Ker) is related to a capacitor-couple electrostatic discharge (ESD) protection circuit for protecting an internal circuit and/or an output buffer of an IC from being damaged by an ESD current. The capacitor-couple ESD protection circuit according to the present invention includes an ESD bypass device for bypassing the ESD current, a capacitor-couple circuit for coupling a portion of voltage to the ESD bypass device, and a potential leveling device for keeping an ESD voltage transmitted for the internal circuit at a low potential level. By using the ESD protection circuit of Ker, the snapback breakdown voltage can be lowered to protect the very thin gate oxide of the internal circuit especially in the submicron CMOS technologies.